CPU-RTL design Engineer, inzip

Key Responsibilities:

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• Strong experience in CPU Core RTL Design: Single-thread / Multi-thread, In-order / Limited Out-of-Order pipelines

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• Must have completed at least one full CPU core development cycle

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• Experience in real-time/high-performance cores (e.g., ARM Cortex-R52 or equivalent)

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• Hands-on in RTL coding (Verilog/SystemVerilog), Timing analysis & closure, Power analysis & optimization

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• Good understanding of: CPU pipeline and Performance, PPA trade-offs

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• Ability to debug and fix timing/power issues and collaborate with PD/Verification teams

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Interested can share cv to Karthick.Viswa@smartsocs.com