IP Design Director, inzip

IP Design Director

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Top40 Semiconductor Organization in the world

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Bangalore

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Role Overview

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We are seeking a Digital Design professional with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions

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Key Responsibilities

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• Design and implement high-performance digital solutions, including RTL development and synthesis.

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• Collaborate with cross-functional teams on IP integration for processor IPs and peripherals

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• Deep knowledge of processor boot process and peripheral implementation with boot firmware inmind

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• Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤

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• 16nm.Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon d

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• ebug.Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verification

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flows

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Basic Qualifications / ExperienceLevel

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• Bachelor’s in Electronics/Electrical engineering (Master's preferred).

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• Minimum 15+ years of digital design experience, with focus on processor, peripherals and full chip implementation.

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• Proven expertise in RTL development, synthesis, and timing closure.

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• Experience with front-end design, gate-level simulations, and design verification.

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• Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.Required

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Expertise

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Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advaned nodes (Experience with front-end design, gate-level simulations, and supporting design verification through multiple ASIC T/O cycles .

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Hands-on experience with processor IP

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(ARM/ARC)Experience of working on PCIe

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is a must.

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Hands-on pre-silicon and post-silicon implementing peripherals for I2

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C/SPI/UART

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Hands-on experience with complex DMA engines and FW interaction.

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Strong proficiency in System Verilog/Verilog and scripting (Python/Perl).

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Experience with block-level and full-chip design at advanced nodes

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(≤ 16nm).

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Silicon bring-up and post-silicon debug experience.

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Familiarity with industry standard simulation, debug, quality checking and synthesis tools Synopsys/Cadence tools and UVM-based design verification.

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Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.

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Preferred Experience

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• Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation is a plus.

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• Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems

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• Experience of working on PCIe/UAL

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• is a big plus.Understanding of PAD design, DFT, and floor planning.

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• Experience in synthesis, and timing closureis a big plus.

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• Experience with NIC, switch, or storage product development.

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• Familiarity with working in design and verification workflows in a CI/CD environment.

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Skils

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microarchitecture

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"rtl design" / "RTL coding" /

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"RTL Development" /"Logic design"

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Synthesis

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"timing closure"

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ARM/ ARC / RISC-V

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PCIe

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Verilog

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Systemverilog (SV )

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UVM

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UAL (UALink)

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NIC

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Switch / Ethernet / "ultra ethernet"

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nvlink

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"Digital design"

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DMA

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"ip design"

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"ip development"

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"ip integraton"

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Contact:Uday

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Mulya Technologies

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muday_

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bhaskar@yahoo.com